Traffic light control buffer



Jan. 31, 1967 R. A. JENSEN ETAL TRAFFIC LIGHT CONTROL BUFFER 2Sheets-Sheet 1 Filed April 28, 1964 FIG.1

CENTRAL PROCESSOR PERIOD DURATION VALUES PERIOD I READ-IN 1 i 17C 18C"'19C 17a 18b 7/CL00K PULSES I 21 20c I 19b I READ IN coIITRoI BUFFERBUFFER I BUFFER CONTROLLER CONTROLLER CONTROLLER (FIG. 2) 5 (FIR 2I \IRb(FIG. 2) 5 I f I 23 I #431:

'IID I IIIcE fl'i Fm ADVANGE EECIHNRWPMADVANCE SYNCHNRgNlZ- 5 T SIGNALSS'GNAL SIGNALS SIGNALS STEPPER STEPPER STEPPER 2T@ -2Tb -2TC 1 27R I 27R27R I 27A2 2N 2M 21s 27c v I 276 j I I, 110 11b 11%:

I vENToRs ROBERT A.JENSEN WILBUR J. LEVINE ATTORNEY Jan. 31, 1967 FiledApril 28, 1964 R. A. JENSEN ETAL TRAFFIC LIGHT CONTROL BUFFER FIG.2

2 Sheets-Sheet L:

L AND INPUT PERIOD DURATION PERM) REALHN OFFSET OFFSET.

VALUES CLOCK READ III CONTROL wg 19M: 'ZIN'PULSES /2o AND 5 1 COUNTERnuauma AN RED PERIOD L REGljzTER I AND 52 52 57 I AND ANDLIL GREENPERIOD REGISTER I 59' -45 WAND 53 HR {73 IIEI) AND 55 I16 3-wAY AMBERPERIOD 5 AND AND EXCLUSIVE REGISTER 1 E OR 2 AND ADVANCE" 3 IIIIIII;GREEII AMBER GI GI 27R 27G J 27A INV 3/ SYNCHRONIZING 27 25 N ADVANCESIGNAL United States Patent 3,302,176 TRAFFIC LIGHT CONTROL BUFFERRobert A. Jensen, Peekskill, and Wilbur J. Levine, Poughkcepsie, N.Y.,assignors to International Business Machines Corporation, New York,N.Y., a corporation of New York Filed Apr. 28, 1964, Ser. No. 363,147 7Claims. (Cl. 340-41) This invention relates to systems for controllingtraffic lights, and more particularly to a buffer controller whichstores commands from a central processor and independ ently guides theoperation of a traffic light.

The high density of trafiic in cities has brought about the use ofhighly complex control systems for controlling tratlic lights to relievethe traffic congestion. Some of the control systems sample the trafiicat various points in the city and process the samples at a centralprocessor to determine the manner in which the individual traffic lightsshould be operated in order to provide the most effective use of theroads.

Other control systems are based on the variation in traffic caused byrush hours and other disturbances during the days. These systems alterthe operation of the traffic lights to accommodate the adjustment intralfic flow during certain times of the day and night.

Often the control system described above employ a central processorwhich processes the data and computes the optimum manner in which thetrafiic lights may be controlled. The central processor is often acomputer or other complex device for performing calculations and storingdata. When the traffic lights are controlled directly by the centralprocessor, a great deal of time and apparatus of the central processoris used to generate control signals to actuate the traffic lights.

Accordingly, it is an object of the present invention to provide animproved traffic control system wherein the traffic lights require lessof the central processors time and apparatus.

It is a further object of the present invention to provide a trafficcontrol system having suflicient flexibility to accommodate changes intraffic density and direction of flow.

Still another object of the present invention is to provide a trafliccontrol system employing a minimum amount of control circuitry and otherapparatus.

It is another object of the present invention to provide a trafiiccontrol system capable of automatically synchronizing the operation ofthe trafiic lights with the control system.

These and other objects of the present invention are accomplished byproviding a buffer controller located between each trafiic light and thecentral processor. The buffer controller stores commands sent by thecentral processor and guides the operation of the associated trafficlight. The same repetitive operation is performed until a new command issent from the central processor.

Since the central process-or provides command signals only when anadjustment is needed, most of the time of a central processor is spentcomputing new sets of trafiic light operations which provide the optimumcontrol over the tratlic flow.

In accordance with the present invention a number of registers, one foreach light energizing period (hereinafter called period) of the lightcycle are included in the buffer controllers. The registers storesignals supplied by the central processor and are read out one by one ina sequential fashion. The values stored in each register determine thelength of the red, green and amber periods of the traflic light.

In accordance with another aspect of the present invention signals arefed back from the trafiic light to the associated buffer controllerindicating the present period of the trafiic light. These signals arecompared with the operation of the buffer controller to determinewhether both are synchronized in operation. If not, the buffercontroller automatically provides a series of signals to advance theoperation of the trafiic light until synchronism is achieved.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

In the drawings:

FIG. 1 is a block diagram illustrating the general op eration of atrafiic control system employing the present invention.

FIG. 2 is a detailed block diagram illustrating the contents of thebuffer controllers shown in FIG. 1.

A traffic control system is shown in FIG. 1. Three traffic lights Ila-care controlled by three bufier controllers 13a-c. The butter controllers13a-c receive commands from a central processor 15 through a group ofconnections 17a-c, 1311-6, 1941-0, 200-0 and 21.

The bufiier controllers 13a-c store the commands from central processor15 and provide signals on a group of lines 23a-c which are connected tostepper switches ZSa-c respectively. Stepper switches 25a-c advance theoperation of trafiic lights Ila-c respectively in response to thesignals on lines 23a-c.

The cycle of operation of trafiic lights Ila-c includes three periods.During the first period, the red indicators designated by the letter Ras shown in FIG. 1 are illuminated. During the second and third periodsthe amber and green indicators designated by A and G are illuminated.Stepper switches ZSa-c advance the operation of the associated trafiiclights. Ila-c so that the indicators are illuminated in a sequentialfashion, i.e., green, amber, red, green, etc. A group of connections27a-c feed back signals identifying which indicatorin the associatedtraffic light Ila-c is illuminated. The signals in connections 27a-c areused to synchronize the operation of butter controllers 13a-c with theoperation of trafiic lights Ila-c in a manner to be described in detailwith reference to FIG. 2.

FIG. 2 illustrates the details of the butter controllers 13a-c shown inFIG. 1. The same designations are applied to the connections shown inFIGS. 1 and 2 with the exception of the letter designations a-c whichare omitted in FIG. 2 since all three buffer controllers 13a-c areidentical.

Three registers 31-33 are shown in FIG. 2 which store 6-bit binarynumbers representing the time duration of the red period, green periodand amber period of the traffic light cycle. Each of the registers 31-33contain six conventional triggers arranged to turn on and off inresponse to six inputs as shown in FIG. 2. Each of the triggers inregisters 31-33 provides an output indicating whether the trigger is onor oil.

Registers 31-33 are supplied with inputs via a group of AND gates 41-43which are opened one at a time by signals on connector 18 from thecentral processor 15. Each of the AND gates 41-43 includes six ANDgates, one for each line in connector 17. When one of the AND gates41-43 is opened the signals on connector 17 are fed to the associatedone of the registers 31-33.

In operation when the time interval of one of the periods of the trafficlight cycle is to be expanded or reduced, commands are sent from thecentral processor 15 via connection 18 to open the corresponding one ofthe AND gates 41-43. At the same time signals are supplied viaconnection 17 setting the six triggers in one of the registers 31-33corresponding to the particular period to be adjusted.

There are 2 or 64 different possible settings of the six triggers ineach of the registers 31-33. Therefore the interval of each of theperiods can be made to vary between 1 and 64 units of time. The numberof triggers in each of the registers 31-33 can be expanded or contractedto suit the requirements of the trafiic control system. Also a varietyof binary codes can be used to convert each period duration into aparticular set of trigger conditions.

The outputs of registers 31-33 are fed through a group of AND gates51-53 which are opened one at a time in a manner to be described laterin the specification. Each of the AND gates 51-53 includes six ANDgates, one for each trigger in the register connected thereto. Theoutput of AND gates 51-53 is fed to an OR gate 55 which provides theinput to a counter 57. The counter 57 includes six conventional triggersarranged to receive the output of one of the registers 31-33, dependingupon which one of the AND gates 51-53 is open. The counter 57 alsoreceives a series of clock pulses on a line 21' originating on line 21from a central processor in a manner to be described in detail later inthe specification.

The interconnections between the six triggers in counter 57 are arrangedso that the clock pulses on line 21 cause the triggers to return to theoff state after a number of clock pulses are received equal to the unitsof time represented by the trigger setting initially placed in counter57. For example where a conventional binary weighted code is assigned toeach position of the registers 31-33 the fifth trigger (designated 5) isassigned a weight of 32 units of time. Therefore when the value 32 isreceived by counter 57 the fifth trigger (designated 5) is turned onwhile the remaining triggers are turned off. After 16 clock pulses arereceived on line 21 all of the triggers are turned to the off state. Thespecific interconnections between the six triggers in counter 57 foraccomplishing this function are well known in the art and are not shownherein. It is also apparent that other weights may be assigned to thetrigger positions in counter 57 so that various other interconnectionsbetween the six triggers in counter 57 may be employed to perform thefunction of counting the number of clock pulses on line 21'corresponding to the number of units of time represented by theparticular initial setting of the six binary triggers in counter 57.

Each of the six triggers in counter 57 supplies an output when thetrigger is off. When all of the triggers in counter 57 are off, an ANDgate 59 provides a pulse on a line 61. The pulse passes through an ORgate 63 to line 23 connected to a stepper switch 25 which advances atraffic light 11 as described above with reference to FIG. 1.

The pulse on line 61 is also fed to a ring circuit 65 having threestages designated 1, 2 and 3. The stages are operated in a sequentialmanner in response to the pulses on line 61, i.e. stages 1, 2, 3, 1,etc. The output of stages 1-3 of ring circuit 65 are connected to ANDgates 51-53 respectively. In operation each time a pulse is applied toline 61 ring circuit 65 advances to the next stage opening another oneof AND gates 51-53 and placing the contents of one of the registers31-33 into counter 57. After counter 57 counts an equivalent number ofclock pulses on line 21, AND gate 59 provides a pulse on line 61 therebyadvancing ring circuit 65 resulting in the transfer of the contents ofanother one of the registers 31-33 into counter 57. Each time the ringcircuit 65 advances a signal appears on line 23 advancing the associatedtraffic light 11.

Ofiset operation Frequently it is desirable to offset the operation ofone traffic light with respect to another. That is, in order to keep avehicle moving along a road through a plurality of intersections thetraflic lights are timed so that when the vehicle arrives at eachintersection the associated traffic light is in the green period of theoperating cycle. This is accomplished by delaying the beginning of thecycle of each traffic light an interval of time equal to the time takenfor the vehicle to travel from one intersection to the nextintersection.

In order to provide an ofiset in the operation of the bufier controller13 shown in FIG. 2 the clock pulses applied on line 21 are delayedbefore arriving at counter 57 via line 21. The offset is needed onlyonce at the beginning of the operation of the buffer controller 13 andneed not be repeated each time the buffer 13 completes a cycle ofoperation.

A counter 57 identical to counter 57 is provided in FIG. 2 to performthe offset operation. The value of the offset is set into counter 57'via connection 19. At the same time the clock pulses on line 21 areblocked from counter 57 by a signal on line 20 which resets a trigger 67inhibiting an AND gate 69 from passing the clock pulses on line 21 tothe input of counter 57 via line 21' The clock pulses on line 21 areapplied to the input of counter 57'. After a number of clock pulses arecounted equal to the offset value supplied via connection 19, AND gate59 is conditioned providing an output which sets trigger 67 therebyopening AND gate 69. The clock pulses on line 21 pass through AND gate69 at this time causing the counter 57 to begin operating in the mannerdescribed above. The delayed commencement of operation of counter 57provides the ofiset necessary to permit continuous flow of trafficthrough a plurality of innersections.

Synchronizing operation When one of the buffer controllers 13 assumescontrol over a traffic light 11 the operation of the traffic light mustbe synchronized with the operation of the ring circuit 65 shown in FIG.2. After this is accomplished the registers 31-33 control the durationof the red, amber and green indicators in the corresponding trafficlight 11.

As described in connection with FIG. 1 signals from the traffic lightare fed back through connection 27 to the buffer controller 13identifying the indicator in traflic light 11 which is illuminated. Asshown in FIG. 2 connector 27 includes three lines 27R, 276 and 27A whichprovide signals to a group of AND gates 71R, 71G, 71A when the red,green or amber indicators are illuminated respectively. Stages 1-3 ofring circuit 65 supply a second input to AND gates 71R, 71G and 71A,respectively. The output of AND gates 71 is applied to a three-wayexclusive OR circuit 73 which provides an output whenever only one inputis provided by AND gates 71.

An inverter '75 supplies OR gate 63 with an inverted form of the outputof exclusive OR circuit 73. In operation inverter 75 supplies a signalto OR gate 63 which in turn advances the operation oftraffic light 11when the ring 65 and traffic light 1.1 are out of synchronism. Forexample the first stage of ring circuit 65 supplies a signal to AND gate71R while the green indicator of trafiic light 11 is illuminated causinga signal to be applied to AND gate 71G. At this time none of the ANDgates '71 supplies a signal to exclusive OR circuit 73 and no outputsignal is supplied to inverter 75. A signal is provided at the output ofinverter 75 which passes through OR gate 63 advancing the operation oftrafiic light 11 from green to amber.

With traffic light 11 now in the amber period AND gate 71A receives asignal from line 27A and inverter 75 supplies a signal to OR gate 63causing stepper switch 25 to continue advancing thereby changing trafficlight 11 from the amber period to the red period. With the ring circuit65 remaining in the first stage and trafiic light 11 in the red periodboth inputs to AND gate 71R are present and a signal is applied toexclusive OR circuit 73. At this time the exclusive OR circuit 73provides a signal to inverter 75 which in turn inverts the signalcausing the absence of a signal at OR gate 63 thereby permitting trafficlight 11 to rest in the red period until counter 57 supplies a signal toOR gate 63.

In summary, what has been shown is a buffer controller circuit 13 whichrelieves the central processor 15 from the continuous control of trafliclights 11. Once the central processor has computed the proper trafficlight cycle, the individual period duration values are set into theregisters 31-33 shown in FIG. 2 along with the particular offset valuewhich is set into counter 57'.

Once the period duration values and offset values are set into thebufler controllers 13 the central processor 15 merely supplies clockpulses on lines 21 causing the buffer controllers 13 to guide thetrafiic lights 11 through the same operating cycle in a repetitivemanner until adjustments of the period duration values become necessary.Further the buffer cont-rollers 13 may be arranged to supply their ownclock pulses thereby achieving completely independent operation.

The buffer controllers 13 may be located near the central processor 15while the stepper switches 25 may be located near the traffic light-s 11in accordance with the preferred embodiment of the present invention.

To prevent failure of the traffic lights 11 the stepper switches 25 maybe provided with an internal control which causes the switches toadvance the trafiic lights 11 in a predetermined manner should theadvance signals on lines 23 fail to arrive after a certain interval oftime. However when the buflfer controllers 13 resume control over thetraffic lights 11 automatic synchronization is accomplished by AND gates71, exclusive OR circuit 73 and inverter 75 in the manner describedabove with regard to FIG. 2.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

What is claimed is:

1. In a traflic light control system, controller means and steppingswitch means, said controller means actuating said switch means foradvancing a traflic light display through a cycle including a pluralityof light energizing periods in response to a series of clock pulses,said controller means comprising:

a plurality of registers, each one capable of storing numbersrepresenting the duration of a light energizing period of said cycle;and

counting means for counting a number of said clock pulses correspondingto the number stored in each one of said registers and for providing acontrol sig nal to advance said traflic light dislay at the completionof each clock pulse count corresponding to said numbers stored in saidregisters.

2. In a traffic light control system, controller means and steppingswitch means, said controller means actuating said switch means foradvancing a trafiic light display through a cycle including a pluralityof light energizing periods in response to a series of clock pulses,said controller means comprising:

a plurality of registers, each one capable of storing numbersrepresenting the duration of a light energizing period of said cycle;

counting means capable of counting a number of said clock pulsescorresponding to numbers applied thereto and providing a control signalto advance said trafiic light display after a number of clock pulsescorresponding to the number applied thereto has been counted; and

gating means for applying the number stored in each 5 register to saidcounting means one by one in a sequential fashion.

3. Apparatus as defined in claim 2 wherein said gating means includesfurther means for applying the number stored in each one of saidregisters to said counting means in response to said control signal.

4. In a traflic light control system, controller means and steppingswitch means, said controller means actuating said switch means foradvancing a t-rafiic light display through a cycle including a pluralityof light energizing periods in response to a series of clock pulses,said controller means comprising:

a plurality of registers, each one capable of storing numbersrepresenting the duration of a light energizing period of said cycle;

counting means capable of counting a number of said clock pulsescorresponding to the number applied thereto;

sensing means for sensing the end of said count and for providing acontrol signal to advance said traffic light display; and

gating means for applying the number stored in each register to saidcounting means one by one in a sequential fashion.

5. Apparatus as defined in claim 4 wherein said gating means includesmeans for applying the number stored in each one of said registers tosaid counting means in response to said control signal.

6. Apparatus as defined in claim 5 further characterized by the additionof offset means for inhibiting the operation of said counting means fora certain number of clock pulses at the beginning of said series ofclock pulses, whereby the cycle of said traffic light display isdelayed.

7. In a traflic light control system for controlling the operation of atraflic light display containing a plurality of indicators, means forsynchronizing the operation of said controller and said trafiic lightdisplay, said means comprising:

timing means having a plurality of stages, each stage corresponding to adifferent one of said indicators,

45 for determining the interval of time between control pulses;

a plurality of AND gates each one having two inputs and an output, oneof said inputs being energized by the operation of one of saidindicators and the other being energized by the corresponding timingmeans stage;

exclusive OR means having inputs connected to said AND gate outputs andhaving an output signal;

stepping switch means for sequentially actuating said indicators inresponse to said output signal, whereby said tralfic light display isadvanced until the indicators and the corresponding timing means stagesare synchronized in operation.

References Cited by the Examiner UNITED STATES PATENTS 65 NEIL C. READ,Primary Examiner.

THOMAS B. HABECKER, Examiner.

1. IN A TRAFFIC LIGHT CONTROL SYSTEM, CONTROLLER MEANS AND STEPPINGSWITCH MEANS, SAID CONTROLLER MEANS ACTUATING SAID SWITCH MEANS FORADVANCING A TRAFFIC LIGHT DISPLAY THROUGH A CYCLE INCLUDING A PLURALITYOF LIGHT ENERGIZING PERIODS IN RESPONSE TO A SERIES OF CLOCK PULSES,SAID CONTROLLER MEANS COMPRISING: A PLURALITY OF REGISTERS, EACH ONECAPABLE OF STORING NUMBERS REPRESENTING THE DURATION OF A LIGHTENERGIZING PERIOD OF SAID CYCLE; AND COUNTING MEANS FOR COUNTING ANUMBER OF SAID CLOCK PULSES CORRESPONDING TO THE NUMBER STORED IN EACHONE OF SAID REGISTERS AND FOR PROVIDING A CONTROL SIGNAL TO ADVANCE SAIDTRAFFIC LIGHT DISPLAY AT THE COMPLETION OF EACH CLOCK PULSE COUNTCORRESPONDING TO SAID NUMBERS STORED IN SAID REGISTERS.